1. Field of the Invention
The present invention relates to a semiconductor device comprising a capacitor having large capacity and low impedance characteristics, and more particularly to a trench type capacitor formed in an SOI (Silicon On Insulator) substrate and a method for manufacturing the trench type capacitor.
2. Description of the Background Art
In a circuit performing a high-speed operation, noises are made by switching a current at a high speed. Such noises are caused by the existence of a parasitic inductance, a parasitic capacitance and a parasitic resistance in each element of the circuit.
In order to reduce the noises, a capacitor having a large capacity and a low impedance is often provided between a DC voltage source such as Vcc and a ground. However, the parasitic resistance existing in an electrode portion of the capacitor hinders the noises from being reduced. In a chip in which an operation is performed in response to a minute signal and an analog circuit and a digital circuit are provided together, particularly, such noises cause serious problems. Accordingly, it is desirable that the capacitor should have a smaller parasitic resistance.
In the case where a capacitor is to be manufactured on a semiconductor substrate, a MOS capacitor or a pn junction capacitor has conventionally been employed.
The MOS capacitor is an element constituting a capacitor by using a MOS gate formed on a semiconductor substrate and an active region formed in the semiconductor substrate. The MOS capacitor is classified into an inversion type and a storage type. The inversion type MOS capacitor is an element having the same structure as the structure of a MOSFET, and designates an element of such a type that a channel layer and a gate electrode in the MOSFET act as both electrodes of the capacitor. On the other hand, the storage type MOS capacitor is an element having such a structure that a MOS gate is formed on an active region provided in a semiconductor substrate, and designates an element of such a type that a gate electrode and the active region act as both electrodes of the capacitor.
Moreover, the pn junction capacitor is an element utilizing a junction capacitance of a pn junction constituted by p-type and n-type active regions formed in the semiconductor substrate.
In the inversion type MOS capacitor, however, a resistance of an inversion layer acting as an electrode is very high, for example, 5 kxcexa9/xe2x96xa1 or more. Therefore, big noises are made during a high-frequency operation. Moreover, in the case where the storage type MOS capacitor is to be formed on an SOI substrate, an active region cannot be formed thickly because an SOI layer provided on a buried oxide film layer (hereinafter referred to as a BOX (Buried Oxide) layer) has a small thickness. Therefore, a parasitic resistance in the active region acting as an electrode has a great value. Furthermore, in the case where the pn junction capacitor is to be formed on the SOI substrate, a parasitic resistance has a great value because an SOI layer has a small thickness in the same manner as the storage type MOS capacitor.
For this reason, a stack type capacitor shown in FIG. 39 has been devised. FIG. 39 is a sectional view showing a memory cell portion and a peripheral circuit portion of a DRAM. A stack type capacitor 65 is employed for the memory cell portion. The memory cell portion comprises a plurality of memory cells. In each memory cell, a MOS transistor constituted by a MOS gate structure including a gate insulating film 54 and a gate electrode 55 and active regions 52 and 53 formed in a semiconductor substrate 50 and the stack type capacitor 65 connected to the active region 53 through a contact plug 58 make a set. The stack type capacitor 65 is constituted by a first electrode 63 connected to the contact plug 58, a dielectric film 62 and a second electrode 64.
Such a stack type capacitor 65 does not have an electrode thereof formed in the semiconductor substrate 50. Therefore, the electrode can have an optional shape, thereby reducing a resistance value. Accordingly, if the stack type capacitor is formed on the SOI substrate, it is possible to eliminate the problem of a parasitic resistance generated by forming an electrode on an SOI layer.
In order to form the electrode of the stack type capacitor 65 to have an optional shape, however, attention should be paid such that the electrode is not short-circuited with a bit line 59 (which is shown in a broken line because it is present on a section other than a section of FIG. 39). For this reason, the stack type capacitor 65 is often formed in a high position seen from a surface of the semiconductor substrate 50.
If the stack type capacitor 65 is formed in a high position, the following drawbacks are caused. For example, in the case where the second electrode 64 of the stack type capacitor 65 and a wiring 66 in the peripheral circuit portion are to be formed at the same time, a conductive material is formed on the dielectric film 62 and an interlayer insulating film 57 and is then subjected to patterning. However, in the case where the second electrode 64 and the wiring 66 are to be patterned by using a photolithography technique, there is a possibility that a difference Y in height between the memory cell portion and the peripheral circuit portion might exceed a depth of focus of a lens (an index indicating an allowable range of focus). If the difference Y in height exceeds the depth of focus, there is a possibility that either or both of the second electrode 64 and the wiring 66 might be subjected to the patterning in a blurred state, thereby obtaining no design dimension.
Moreover, in the case where the wiring 66 is to be formed simultaneously with the formation of the bit line 59 and the second electrode 64 is to be formed simultaneously with the formation of a wiring 67 in order to avoid the problems of the depth of focus, an aspect ratio of a contact plug 67a of the wiring 67 is increased. Consequently, it is hard to form a via hole for the contact plug 67a and to bury a conductive material in the via hole.
There has been devised a trench type capacitor having such a structure that a capacitor is not formed on a semiconductor substrate but is fabricated in the semiconductor substrate differently from the stack type capacitor.
FIG. 40 is a sectional view showing the prior art described in U.S. Pat. No. 5,759,907 as an example of the trench type capacitor. FIG. 40 illustrates a trench type capacitor constituted by a dielectric film 119 buried in a trench 118, an SOI layer 117 and an impurity implantation region 116 which act as a first electrode, and a polysilicon 120 acting as a second electrode. According to this technique, the trench 118 is formed deeply to reach a semiconductor substrate 110 through a BOX layer 111 and the SOI layer 117. Therefore, a contact area of each electrode and the dielectric film can be increased and a large capacity can be implemented. Moreover, the impurity implantation region 116 acting as the first electrode and the polysilicon 120 acting as the second electrode can be formed thickly or largely. Thus, the problem of a parasitic resistance can be restrained.
In the case where a rays enter the semiconductor substrate 110 to generate a large number of electronxe2x80x94hole pairs in the trench type capacitor shown in FIG. 40, their electric charges move to a DC voltage source or a ground through the impurity implantation region 116, the polysilicon 120 in a trench 118a and a metal wiring 125. Consequently, there is a problem in that a fluctuation in a source voltage is caused. In other words, a tolerance to soft errors is small. For example, when neutron rays are irradiated on a very small amount of boron 10B present in BPSG to be used as an interlayer insulating film, the boron 10B generates a rays having a low energy of 1 MeV or less so that the soft errors are made. The maximum quantity of electric charges are generated within a range of the xcex1 rays. Since the range of the xcex1 rays having an energy of 1 Mev is about 5 xcexcm, for example, the largest number of electric charges are generated in the semiconductor substrate in a position where a depth from the interlayer insulating film is almost equal to the range.
In the trench type capacitor shown in FIG. 40, moreover, the polysilicon 120 acting as the electrode and the metal wiring 125 are directly provided in contact with each other. Therefore, there is a problem in that a contact resistance is raised, resulting in an increase in a parasitic resistance value of the capacitor.
In order to enhance a soft error tolerance, it can also be supposed that a trench type capacitor is formed on a trench which does not penetrate the BOX layer in the SOI substrate. Consequently, even if radioactive rays enter to generate electric charges in the semiconductor substrate, the BOX layer becomes an insulating film for preventing the movement of the electric charges.
As the trench type capacitor having the above-mentioned structure, for example, Japanese Patent Application Laid-Open Gazette No. P02-288263 has described the art. FIG. 41 is a sectional view showing the art. FIG. 41 illustrates a trench type capacitor constituted by a first electrode 228, a dielectric film 229 and a second electrode 230 which are buried in a trench 227 in a semiconductor substrate 220. The trench type capacitor is formed without penetrating a BOX layer 221. Therefore, the generation of soft errors can be prevented.
In the structure of the trench type capacitor shown in FIG. 41, however, an A portion of the first electrode 228 is protruded in a transverse direction from a width of the trench 227. Consequently, a distance B between the first electrode 228 and a gate electrode 225 of a MOSFET is reduced. There is a possibility that a leakage current might be generated therebetween. Moreover, since the portion A is protruded, area penalty (a degree of an impediment to the effective utilization of a substrate surface area) is increased. In a DRAM, particularly, a large number of capacitors are formed. Therefore, a slight increase in the area penalty also affects an integration degree.
Furthermore, there is the protruded portion A. Therefore, an area of the first electrode 228 on an end of the capacitor is increased. Consequently, a fringe capacitance C12 between the first electrode 228 and the second electrode 230 on the end of the capacitor is increased so that big noises are made.
In the art, a contact resistance between an electrode and a metal wiring is not taken into consideration.
In order to solve the above-mentioned problems, it is an object of the present invention to implement a semiconductor device comprising a trench type capacitor having such a structure that a soft error tolerance is excellent, a contact resistance between an electrode and a metal wiring has a small value, a fringe capacitance on an end is reduced and area penalty is not increased, and a method for manufacturing the semiconductor device.
A first aspect of the present invention is directed to a semiconductor device comprising a semiconductor substrate, a first layer of insulation formed on the semiconductor substrate, a second layer including at least a semiconductor layer formed on the first layer, a trench provided with an opening having a predetermined width on a surface of the second layer and reaching the first layer without penetrating the first layer, and a capacitor including a first electrode, a dielectric film and a second electrode which are formed in the trench, wherein an end of the capacitor is positioned in the opening of the trench.
A second aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, further comprising a contact plug connected to the second electrode and set within a range of the predetermined width.
A third aspect of the present invention is directed to the semiconductor device according to the second aspect of the present invention, further comprising a wiring to be connected to the contact plug, a metal silicide being formed in a portion of the contact plug which is connected to the wiring.
A fourth aspect of the present invention is directed to the semiconductor device according to the third aspect of the present invention, wherein a metal nitride film is formed between the metal silicide and the wiring.
A fifth aspect of the present invention is directed to the semiconductor device according to any of the second to fourth aspects of the present invention, further comprising an insulator for covering the end of the capacitor.
A sixth aspect of the present invention is directed to the semiconductor device according to the fifth aspect of the present invention, wherein the insulator includes a first insulating layer which is provided in contact with the end of the capacitor and has a relatively low degree of mismatching of crystal lattice between the first insulating layer and the first electrode and between the first insulating layer and the second electrode, and a second insulating layer which is formed on the first insulating layer and has a relatively high degree of the mismatching of the crystal lattice between the second insulating layer and the first electrode and between the second insulating layer and the second electrode.
A seventh aspect of the present invention is directed to the semiconductor device according to any of the first to sixth aspects of the present invention, further comprising an active region connected to the first electrode in the second layer, the active region constituting a part of a transistor or being connected to the transistor.
An eighth aspect of the present invention is directed to a method for manufacturing a semiconductor device comprising a first step of preparing a semiconductor substrate having a first layer of insulation formed on a surface of the semiconductor substrate and a second layer including at least a semiconductor layer formed on the first layer, a second step of forming a first trench provided with an opening having a predetermined width on a surface of the second layer and reaching the first layer without penetrating the first layer, a third step of forming a first conductive film over a whole surface of the semiconductor substrate, a fourth step of forming a dielectric film on the first conductive film, a fifth step of forming a second conductive film on the dielectric film, and a sixth step of removing portions of the first conductive film, the dielectric film and the second conductive film which are provided on the surface of the second layer.
A ninth aspect of the present invention is directed to the method for manufacturing a semiconductor device according to the eighth aspect of the present invention, further comprising a seventh step of forming a third layer of insulation on the second layer, the first conductive film, the dielectric film and the second conductive film, an eighth step of forming, on the third layer, a second trench provided with an opening set within a range of the predetermined width on a surface of the third layer and connected to the second conductive film, a ninth step of forming a third conductive film over the whole surface of the semiconductor substrate, and a tenth step of removing a portion of the third conductive film provided on the surface of the third layer.
A tenth aspect of the present invention is directed to the method for manufacturing a semiconductor device according to the ninth aspect of the present invention, further comprising an eleventh step of forming a metal film to cover the third conductive film, a twelfth step of heat treating the third conductive film and the metal film, a thirteenth step of removing the metal film which has not reacted to the third conductive film, and a fourteenth step of forming a fourth conductive film on the third conductive film which has reacted to the metal film and patterning the fourth conductive film by using a photolithography technique.
An eleventh aspect of the present invention is directed to the method for manufacturing a semiconductor device according to the tenth aspect of the present invention, wherein the fourteenth step also includes a step of forming a metal nitride film between the third conductive film which has reacted to the metal film and the fourth conductive film.
A twelfth aspect of the present invention is directed to the method for manufacturing a semiconductor device according to any of the ninth to eleventh aspects of the present invention, wherein the eighth step includes a step of forming, on the third layer, a third trench having the same width as the predetermined width and positioned above the first trench, and then forming a fourth layer of insulation covering the third layer and carrying out anisotropic etching on the fourth layer, thereby forming the second trench.
A thirteenth aspect of the present invention is directed to the method for manufacturing a semiconductor device according to the twelfth aspect of the present invention, further comprising a fifteenth step of forming a fifth layer of insulation by heat treating respective surfaces of the first conductive film, the dielectric film and the second conductive film which are exposed to the opening after the sixth step and before the seventh step.
A fourteenth aspect of the present invention is directed to the method for manufacturing a semiconductor device according to the thirteenth aspect of the present invention, further comprising a sixteenth step of forming a sixth layer on the second layer and the fifth layer after the fifteenth step and before the seventh step.
A fifteenth aspect of the present invention is directed to the method for manufacturing a semiconductor device according to any of the eighth to fourteenth aspects of the present invention, wherein the first step includes a step of forming, in the second layer, an active region and a transistor connected to or including as a part the active region.
According to the first aspect of the present invention, it is possible to obtain a trench type capacitor having such a structure that a soft error tolerance is excellent, a fringe capacitance is reduced on an end and area penalty is not increased. Moreover, heat accumulated in the semiconductor substrate and the first layer can be discharged to the outside by the capacitor.
According to the second aspect of the present invention, the contact plug does not increase the area penalty.
According to the third aspect of the present invention, in the case where the wiring is formed of a metal and the contact plug is formed of a polysilicon, a value of a contact resistance between the wiring and the contact plug can be decreased. Moreover, lines of electric force sent from other wirings can be prevented from entering the second electrode.
According to the fourth aspect of the present invention, in the case where the wiring is formed of a metal and the contact plug is formed of a polysilicon, it is possible to prevent the metal constituting the wiring and a metal and silicon in the metal silicide from mutually moving and reacting to generate foreign matters.
According to the fifth aspect of the present invention, it is guaranteed that the contact plug is not connected to the first electrode but is connected to the second electrode.
According to the sixth aspect of the present invention, also in the case where a material having a high degree of the mismatching of the crystal lattice between the first and second electrodes is used for the second insulating layer, it is possible to prevent an interface state from being generated between the insulator and the end of the capacitor.
According to the seventh aspect of the present invention, the capacitor and the transistor can be used as a memory cell of a DRAM, for example.
According to the eighth aspect of the present invention, the semiconductor device in accordance with the first aspect of the present invention can be manufactured. Moreover, the second layer can be caused to function as a stopper at the sixth step by using, for the second layer, a material having selectivity for each of the first conductive film, the dielectric film and the second conductive film.
According to the ninth aspect of the present invention, the semiconductor device in accordance with the second aspect of the present invention can be manufactured. Moreover, the second conductive film can be caused to function as a stopper at the eighth step by using, for the second conductive film, a material having selectivity for the third layer. Furthermore, the third layer can be caused to function as a stopper at the tenth step by using, for the third layer, a material having selectivity for the third conductive film.
According to the tenth aspect of the present invention, the semiconductor device in accordance with the third aspect of the present invention can be manufactured.
According to the eleventh aspect of the present invention, the semiconductor device in accordance with the fourth aspect of the present invention can be manufactured.
According to the twelfth aspect of the present invention, the semiconductor device in accordance with the fifth aspect of the present invention can be manufactured. By adjusting a thickness of the fourth layer and etching conditions, moreover, the second trench is not connected to the first conductive film but can be connected to the second conductive film. Furthermore, the second conductive film can be caused to function as a stopper at the eighth step by using, for the second conductive film, a material having selectivity for the fourth layer.
According to the thirteenth aspect of the present invention, the semiconductor device in accordance with the sixth aspect of the present invention can be manufactured. Moreover, even if foreign matters remain in the opening of the first trench, they can be insulated by a heat treatment. Thus, it is guaranteed that the first and second conductive films can be prevented from being short-circuited.
According to the fourteenth aspect of the present invention, the sixth layer can be caused to function as a stopper during the formation of the third trench by using, for the sixth layer, a material having selectivity for the third layer.
According to the fifteenth aspect of the present invention, the semiconductor device in accordance with the seventh aspect of the present invention can be manufactured.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.